Design Workshop Technologies - Electronic Design Automation
Design Workshop software for design of microelectronics and photonics computer components
    XDRC Features
    Standard DRC Features

Feature Highlights

Todayís process technologies require layout tools be able to deal with smaller geometries, more data and more complex types of checks. The motivation behind dw-2000ô XDRC is to supply designers with a physical verification tool that can verify the design rules of the most advanced process technologies. XDRC also provides designers with the flexibility to combine these rules into complex scripts, making it the ultimate tool for designing Optoelectronic, Analog, Mixed Signal and RF devices. XDRCís main features are:
Large Set of Rules

XDRCís large set of rules enable the designer to describe very complex checks that may be required for specific technology requirements. This is useful for designers who need to add "in-house" rules to the already complex foundry scripts.

Layer Density Rules

Foundries impose density specifications for processes with feature sizes smaller than 0.5 microns. Failure to meet these specifications can result in the entire fabrication run being rejected by the foundry. XDRC includes commands that can compute density on a defined area, or an entire design, to ensure that these requirements are met.

Off-grid and Acute Rules

Certain processes require that all geometries (or objects) be on a specified grid or have no segments form acute angles. XDRC includes rules for these specified checks along with many other rules that can be applied to geometries, such as area and perimeter.

Antenna Rules

Deep submicron process technologies mean smaller gate sizes and more metals added to a chip. This causes the antenna effect to have a more significant impact on manufacturing yields. XDRC provides an easy way to identify antenna rule violations and the offending geometries.

End-of-Line Rules

XDRC is a versatile tool that allows designers to verify asymmetric rules. An example where an asymmetric rule is required is the end-of-line check. Contacts or vias that are placed at the very end of a line are in danger of not being filled. XDRC offers the ability to verify these rules.


With XDRC, designers are able to translate popular design rule scripts into dw-2000ís own GPE scripting language. This enables designers to quickly continue verifying new designs with their existing rule decks. Please enquire about our ability to help you convert existing decks to XDRC.

Integration with dw-2000

XDRC can be used with the dw-2000 Layout Editor to provide all the flexibility and power of a full-featured back end verification tool. With the Layout Editor the designer has an interface for easy error navigation and correction, and can use the scripting language to write complex rules' scripts. dw-2000 represents DRC errors with color-coded markers (tags) placed directly on the offending errors. Depending on the options you specify, XDRC automatically zooms in on error areas. Also, since each error can be identified by a label (via scripting), you can assign meaningful names to represent an error, thereby simplifying complex error recognition. Although designed to be used with the dw-2000 Layout Editor, XDRC is also operable as a stand-alone tool.